1. Field of the Invention
The present invention relates to semiconductor memory device fabrication and, more particularly, to a method for fabricating a crown-type capacitor whose lower electrode (storage electrode) is formed using a triple-layer technique.
2. Discussion of the Related Art
In the manufacture of semiconductor memory devices, cell capacitance is inherently reduced with any decrease in memory cell area, which is required for higher levels of DRAM integration. As the primary obstacle to increased integration, reduced cell capacitance results in a drop off in the ability of a memory cell to read out data, causes difficulties in low-voltage operation, and tends to increase soft error rates. Therefore, to realize highly integrated semiconductor memory devices, e.g., DRAMs, the cell capacitance problem must be addressed.
Recently developed three-dimensional capacitors may be classified in accordance with the structure of the lower electrode of the capacitor. Examples include pin-type, box-type, cylindrical, and crown-type lower electrodes. In particular, the crown-type capacitor has received much attention in research due to its suitability for semiconductor devices having a design rule of 0.20 .mu.m or less. Conventionally, a single-layer technique is used in forming the lower electrode of a crown-type capacitor.
FIGS. 1 to 5 are cross-sectional views illustrating various steps for fabricating a crown-type capacitor of a semiconductor device in accordance with a conventional technique.
To begin with, a plurality of word lines (not shown) are formed on a semiconductor substrate (not shown), and then an interlevel dielectric layer 10 which is composed of borophosphorous silicate glass (BPSG) and comprises a cell region and a periphery region of a substrate. After a nitride film (not shown) is deposited over the entire structure on which the bit lines 20 are formed, the nitride film in the periphery region is anisotropically etched until the interlevel dielectric layer 10 is exposed.
As a result, the bit lines 20 in the cell region are capped with the nitride film, whereas those in the periphery region are covered with the nitride film only on their sidewalls in order to form spacers. The nitride film allows a silicon conductive layer (to be described with respect to FIG. 2) to be self-aligned with the cell region while in contact with the interlevel dielectric layer 10 but not so as to create an electrical short between the bit lines 20.
Thereafter, a first oxide layer 30, also composed of undoped silicate glass (USG) or BPSG, is deposited over the entire structure obtained after etching the nitride film, so as to fill the gaps between the bit lines 20. An anti-reflective coating (ARC) layer 40 is then formed over the first oxide layer 30.
Referring to FIG. 2, first, the ARC layer 40 and the first oxide layer 30 are anisotropically etched until the interlevel dielectric layer 10 of the cell region is exposed, thereby forming via-holes. Next, a silicon conductive layer 50 for forming the lower electrode is deposited over the entire structure having the via-holes formed therein. The silicon conductive layer 50 is electrically connected to the semiconductor substrate through a contact plug (not shown) formed in the interlevel dielectric layer 10.
At this time, as described above, the silicon conductive layer 50 is self-aligned and in contact with the interlevel dielectric layer 10 but not so as to electrically short the bit lines 20. A second oxide layer 60 is then deposited over the entire structure resulting from the deposition of the silicon conductive layer 50, so as to fill the remainder of the via-holes, i.e., atop the formation of the silicon conductive layer.
Referring to FIGS. 3 and 4, the second oxide layer 60 is firstly subjected to isotropic etching to expose the top surface of the silicon conductive layer 50. In this case, the second oxide layer 60 may remain over the silicon conductive layer 50 in the periphery region. Thereafter, the silicon conductive layer 50 and ARC layer 40 are isotropically etched until the top surface of the first oxide layer 30 is exposed, thereby completing a lower electrode 50a which serves as the capacitor's storage electrode.
FIG. 5 illustrates the problem of the conventional art. That is, the oxide material of the layers 30 and 60 is removed by a wet etching, which also results in the removal of surface portions of the interlevel dielectric layer 10 thus creating "loss" areas A. As a consequence, other parts of the interlevel dielectric layer 10 tend to fill the loss area A during a subsequent annealing process, which causes a shifting of the bit lines 20 and may even result in the collapse of the bit lines and an electrical connection (shorting) with nearby conductors.
To prevent this phenomenon, it has been suggested to leave a predetermined thickness of the first oxide layer 30 after the wet etching step, that is, to carry out an incomplete etching step. In this case, however, minute cracks may form in the periphery region of the first oxide layer 30, which is left relatively thin, due a thermal stress caused by the annealing process. In addition, an incomplete etching of the first oxide layer 30 results in the incomplete removal of the second oxide layer 60. This excess (unremoved) portion of the second oxide layer 60 causes imperfections in the inner sidewall surface of the lower electrode 50a, resulting in reduced reliability of the electrical characteristics of the capacitor.
It is preferred to form the first oxide layer 30 using a suitable material, one which does not crack, and to etch the layer so as to leave at least some of the material intact. However, it has proved impossible to do so while completely removing the second oxide layer 60. More particularly, the first oxide layer 30 should, without cracking, completely fill the gaps between the bit lines 20 without a void. In this regard, the conventional art suffers from the problem that no suitable material has been found to satisfy the conditions of the complete removal of the second oxide layer 60 and filling the gaps without the void.
As described above, the conventional method for fabricating a crown-type capacitor, which forms the lower electrode using a single layer, i.e., the first oxide layer 30, cannot completely overcome the shifting of the bit lines 20 by the flowing of the interlevel dielectric layer 10 when the lower electrode 50a is formed, and the subsequent collapse or shorting.